
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:15:43 06/08/2009
-- Design Name:   PRM_time_1
-- Module Name:   E:/projects/ISE 9.2/PR/reconfig/time/octaver/octaver_tb.vhd
-- Project Name:  octaver
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: PRM_time_1
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY octaver_tb_vhd IS
END octaver_tb_vhd;

ARCHITECTURE behavior OF octaver_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT PRM_time_1
	PORT(
		clk : IN std_logic;
		clk_48k : IN std_logic;
		reset : IN std_logic;
		control_in : IN std_logic_vector(7 downto 0);
		PCM_data_in_right : IN std_logic_vector(15 downto 0);
		PCM_data_in_left : IN std_logic_vector(15 downto 0);          
		control_out : OUT std_logic_vector(3 downto 0);
		PCM_data_out_right : OUT std_logic_vector(15 downto 0);
		PCM_data_out_left : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL clk_48k :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';
	SIGNAL control_in :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL PCM_data_in_right :  std_logic_vector(15 downto 0) := (others=>'0');
	SIGNAL PCM_data_in_left :  std_logic_vector(15 downto 0) := (others=>'0');

	--Outputs
	SIGNAL control_out :  std_logic_vector(3 downto 0);
	SIGNAL PCM_data_out_right :  std_logic_vector(15 downto 0);
	SIGNAL PCM_data_out_left :  std_logic_vector(15 downto 0);
	
	type table is array (0 to 127) of std_logic_vector(15 downto 0);
	constant LOOKUP				: table := ("0000000000000000",
	                                       "0000011001000111",
	                                       "0000110010001011",
	                                       "0001001011001000",
	                                       "0001100011111000",
	                                       "0001111100011001",
	                                       "0010010100101000",
	                                       "0010101100011111",
	                                       "0011000011111011",
	                                       "0011011010111010",
	                                       "0011110001010110",
	                                       "0100000111001110",
	                                       "0100011100011100",
	                                       "0100110000111111",
	                                       "0101000100110011",
	                                       "0101010111110101",
	                                       "0101101010000010",
	                                       "0101111011010111",
	                                       "0110001011110010",
	                                       "0110011011001111",
	                                       "0110101001101101",
	                                       "0110110111001010",
	                                       "0111000011100010",
	                                       "0111001110110101",
	                                       "0111011001000001",
	                                       "0111100010000100",
	                                       "0111101001111101",
	                                       "0111110000101001",
	                                       "0111110110001010",
	                                       "0111111010011101",
	                                       "0111111101100010",
	                                       "0111111111011000",
														"0111111111111111",
	                                       "0111111111011000",
	                                       "0111111101100010",
	                                       "0111111010011101",
	                                       "0111110110001010",
	                                       "0111110000101001",
	                                       "0111101001111101",
	                                       "0111100010000100",
	                                       "0111011001000001",
	                                       "0111001110110101",
	                                       "0111000011100010",
	                                       "0110110111001010",
	                                       "0110101001101101",
	                                       "0110011011001111",
	                                       "0110001011110010",
	                                       "0101111011010111",
	                                       "0101101010000010",
	                                       "0101010111110101",
	                                       "0101000100110011",
	                                       "0100110000111111",
	                                       "0100011100011100",
	                                       "0100000111001110",
	                                       "0011110001010110",
	                                       "0011011010111010",
	                                       "0011000011111011",
	                                       "0010101100011111",
	                                       "0010010100101000",
	                                       "0001111100011001",
	                                       "0001100011111000",
	                                       "0001001011001000",
	                                       "0000110010001011",
	                                       "0000011001000111",
														"1111111111111111",
	                                       "1111100110111000",
	                                       "1111001101110100",
	                                       "1110110100110111",
	                                       "1110011100000111",
	                                       "1110000011100110",
	                                       "1101101011010111",
	                                       "1101010011100000",
	                                       "1100111100000100",
	                                       "1100100101000101",
	                                       "1100001110101001",
	                                       "1011111000110001",
	                                       "1011100011100011",
	                                       "1011001111000000",
	                                       "1010111011001100",
	                                       "1010101000001010",
	                                       "1010010101111101",
	                                       "1010000100101000",
	                                       "1001110100001101",
	                                       "1001100100110000",
	                                       "1001010110010010",
	                                       "1001001000110101",
	                                       "1000111100011101",
	                                       "1000110001001010",
	                                       "1000100110111110",
	                                       "1000011101111011",
	                                       "1000010110000010",
	                                       "1000001111010110",
	                                       "1000001001110101",
	                                       "1000000101100010",
	                                       "1000000010011101",
	                                       "1000000000100111",
														"1000000000000000",
	                                       "1000000000100111",
	                                       "1000000010011101",
	                                       "1000000101100010",
	                                       "1000001001110101",
	                                       "1000001111010110",
	                                       "1000010110000010",
	                                       "1000011101111011",
	                                       "1000100110111110",
	                                       "1000110001001010",
	                                       "1000111100011101",
	                                       "1001001000110101",
	                                       "1001010110010010",
	                                       "1001100100110000",
	                                       "1001110100001101",
	                                       "1010000100101000",
	                                       "1010010101111101",
	                                       "1010101000001010",
	                                       "1010111011001100",
	                                       "1011001111000000",
	                                       "1011100011100011",
	                                       "1011111000110001",
	                                       "1100001110101001",
	                                       "1100100101000101",
	                                       "1100111100000100",
	                                       "1101010011100000",
	                                       "1101101011010111",
	                                       "1110000011100110",
	                                       "1110011100000111",
	                                       "1110110100110111",
	                                       "1111001101110100",
	                                       "1111100110111000");
														
	signal index : integer := 0;
BEGIN                                  

	-- Instantiate the Unit Under Test (UUT)
	uut: PRM_time_1 PORT MAP(
		clk => clk,
		clk_48k => clk_48k,
		reset => reset,
		control_in => control_in,
		control_out => control_out,
		PCM_data_in_right => PCM_data_in_right,
		PCM_data_in_left => PCM_data_in_left,
		PCM_data_out_right => PCM_data_out_right,
		PCM_data_out_left => PCM_data_out_left
	);

	control_in <= "10001011";

	clk_100M_p : process
	begin
		clk <= not clk;
		wait for 5 ns;
	end process;

	clk_48k_p : process
	begin
		clk_48k <= not clk_48k;
		wait for 10417 ns;
	end process;

	process(clk_48k)
	begin
		if reset = '0' then
			PCM_data_in_left <= (others => '0');
			index <= 0;
		elsif clk_48k'event and clk_48k = '1' then
			PCM_data_in_left	<= LOOKUP(index);
			if index = 127 then
				index <= 0;
			else
				index <= index + 1;
			end if;
		end if;
	end process;

	reset_p : PROCESS
	BEGIN
		reset <= '0';
		wait for 100000 ns;
		reset <= '1';
		wait; -- will wait forever
	END PROCESS;

END;
